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A Senior Package Design Engineer with extensive hands-on experience using Cadence APD/Allegro tools, experience with Ansys/AutoCAD and SI/PI Simulation tools will join a thriving Semiconductor scale-up enabling the build of scalable, energy efficient AI systems Worldwide.
The Senior Package Design Engineer will undertake all package design activities with cross functional team collaboration – delivering high speed interconnect systems; ensuring cost effective methodologies are incorporated, completing verification of electrical characteristics of the package and providing support to assembly related activities.
The Senior Package Design Engineer should possess the following:
* 5+ years’ Semiconductor Package design using Cadence APD/Allegro tools
* Expertise with Cadence (Virtuoso/Extract IM/Power DC) / Ansys SW tools.
* Using AutoCAD.
* Experience of IC physical layout.
* Minimum of Bachelors Electronic Engineering Degree.
* A basic understanding of Thermal and mechanical behaviour of IC Packages.
This exciting Semiconductor Company will offer a highly competitive salary package to the successful Senior Package Design Engineer